A systematic methodology to identify delay marginalities in a design during first-silicon validation

In this paper, we present a systematic framework to identify delay marginalities in a design during first silicon validation. Our method guarantees the excitation of the worst-case delay of the chips in the first silicon batch without introducing any pessimism. It embodies several innovations, including a resilient gate delay model to capture process variations, new conditions that vectors must satisfy to invoke the maximum delay of a target path, and a new approach to generate multiple vectors (vector-spaces) guaranteed to invoke the worst-case delay of the target path. We also present extensive experimental results for benchmark circuits to demonstrate the effectiveness of our method.